1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, it relates to an electrically erasable and programmable non-volatile semiconductor device.
2. Description of the Related Art
Electrically erasable and programmable ROMs (EEPROM) are well known as an electrically erasable and programmable non-volatile memory. The EEPROM, similar to the EPROM, stores information responsive to charges stored in the memory cell and uses the tunnel phenomenon to transfer charges in its programming and erasing processes wherein electrons are sent to and received by a floating gate using a tunnel current which passes through a thin tunnel insulating film on the substrate of the device.
FIG. 1A is a pattern plan showing an arrangement of one cell of a conventional EEPROM, FIG. 1B is a sectional view taken along a line IB--IB in FIG. 1A, FIG. 1C is a sectional view taken along a line IC--IC in FIG. 1A, and FIG. 1D is a sectional view showing a logic transistor which is a component formed on the same substrate as that of the memory cell to form a large-scale logic circuit, such as a gate array.
In FIGS. 1A through 1D, the cell which represents 1 bit (unit of information) comprises a selection transistor 41 for preventing half-selection and a memory transistor 42 for storing information. Namely, a selection gate 46 and a floating gate 47 are formed, adjacent to each other and with a gates insulating film 45 interposed between a semiconductor substrate 43 and them, at an element region separated from each other on the substrate 43 by elements separating regions 44, a control gate 49 is also formed there with an interlayer insulating film 48 interposed between the floating gate 47 and control gate 49. Reference numeral 50 denotes a diffusion layer which has a conductivity type opposite that of the substrate, and reference numeral 51 is an aluminium wiring formed on the interlayer insulating film.
Information is stored in the electrically floating gate 47 of the memory transistor 42. The memory transistor is on- and off-controlled responsive to electrons stored and missed in the floating gate 47. The region of a tunnel insulating film 52 which corresponds to a thinner part (about 100.ANG., for example) of the gates insulating film 45 is used to store and miss electrons in the floating gate 47. Namely, tunnel current flows through the tunnel insulating film 52 due to bias added between the control gate 49 and the diffusion layer 50. Electrons are thus sent to and received by the floating gate 47.
In the case of the logic transistor which serves to form the large-scale logic circuit and which is shown in FIG. 1D, a gate electrode 53 is formed on the same substrate 43 with the gates insulating film 45 interposed between the substrate and the electrode, and the diffusion region which has a conductivity opposite that of the substrate is formed separating from the gate electrode 53.
An electric current needed to write and erase information in and from the cell may be small in the case of the EEPROM which uses the tunnel phenomenon. Most of the EEPROMs include a boosting circuit (not shown) to create high voltage in the elements, and they are made operative by a single power source (about 5V, for example).
In the case of the above-described conventional example, high voltage (about 20V) is added from the boosting circuit to the memory cell and the gate electrode of the selection transistor shown in FIGS. 1A through 1C and common power source voltage (about 5V) is added to the gate electrode of the logic transistor shown in FIG. 1D.
In spite of the fact that these voltages are used, however, the gates insulating film has the same film thickness (h) (about 450.ANG., for example) except in the region of the tunnel insulating film 52. In short, the gates insulating film used by the conventional EEPROMs is formed to have a film thickness of about 450.ANG. in all of the transistors of the high voltage and 5V types except at the tunnel insulating film whose film thickness is about 100.ANG..
When arranged in this manner, the logic transistor has a film thickness of 450.ANG. which is the same as that of the high voltage gates insulating film, although its operation voltage is 5V supplied from the common power source. This causes the following problems:
Firstly, operation speed becomes low.
Current I.sub.DS between the drain and the source is usually calculated to assume the operation speed of a single transistor. As this I.sub.DS becomes larger, the operation speed becomes higher. The I.sub.DS can be expressed as follows at the saturated region of the transistor usually used: ##EQU1## wherein C.sub.OX =.epsilon..sub.O .epsilon..sub.I S / d.sub.I, and wherein .mu. represents the mobility in channel, C.sub.OX the capacity of gates insulating film, W the width of channel, L the length of channel, V.sub.GS voltage between the drain and the source, V.sub.TH the threshold value, d.sub.I the film thickness of insulating film, .epsilon..sub.0 the dielectric constant in vacuum, .epsilon..sub.I the relative dielectric constant of insulating film, and S the area of electrode.
According to the above equation (1), I.sub.DS is decreased as the film thickness d.sub.I of insulating film becomes larger. As the gates insulating film becomes thicker, therefore, the operation speed of the transistor becomes lower.
Secondly, there is the problem of short channel effect which has become a new obstacle in the course of integrating the circuit as much as possible. The approximate equation of this short channel effect can be expressed as follows: ##EQU2## wherein C.sub.I =.epsilon..sub.O .epsilon..sub.I S / d.sub.I and L=[(Xj+Wj).sup.2 -Wc.sup.2 ].sup.1/2 -Xj and wherein .DELTA.V.sub.TH denotes the changed part of V.sub.TH caused by the short channel effect, .epsilon..sub.S the relative dielectric constant of silicon, q the amount of charge, N.sub.A the density of acceptor impurity, .psi.S the surface potential, C.sub.I the capacity of insulating film, Leff the effective length of channel, Xj the depth of junction, Wj the width of junction depletion layer, and Wc the width of channel depletion layer.
According to the above equation (2), V.sub.TH becomes larger and the short channel effect becomes higher as the film thickness of the insulating film becomes larger. This prevents the circuit from being integrated as much as possible.
In the case of the conventional EEPROMs, the gates insulating film of each of transistors is formed to have the same film thickness except the region of the tunnel insulating film without taking voltages used into consideration.
This prevents the operation speed of the circuit located in the periphery of the memory cell and that of the large-scale logic circuit, both of them being made operative by the power source voltage, from being made higher. This also prevents the circuits from being integrated as much as possible because the short channel effect becomes high.